``TSMC needs a physical verification solution up to the challenge of rapidly verifying multi-million transistor designs to give our customers the fastest possible turn-around time. Files are updated within seven days of a TSMC process rules specification revision, ensuring customers' ability to keep up with the rapid pace of process technology evolution. This translates into much faster completion of design and tape-out.Ĭustomers can download high quality 0.18-micron, 0.22-micron, 0.25-micron and 0.35-micron Calibre rule files from the TSMC-Online customer information Web site at. Customers of TSMC and Mentor Graphics can now complete multiple physical verification runs per day on SoC designs incorporating hundreds of millions of transistors. TSMC adopted the Calibre product line because it delivers immediate availability of world-class Turn-Around Time (TAT) for large 0.25/0.18-micron System-on-Chip (SoC) designs fabricated across a variety of process technologies, including advanced logic processes, mixed-signal processes and various embedded memory processes. ![]() 14 - Mentor Graphics Corporation (Nasdaq: MENT) and Taiwan Semiconductor Manufacturing Corporation (TSMC) today jointly announced that TSMC has selected the Mentor Graphics Calibre® product line as the physical verification tool within its netlist sign-off flow for deep submicron designs. ![]() IP News TSMC Adopts Mentor Graphics Calibre Physical Verification Tool Into Its SoC Design Flow
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